Data buses are used in integrated circuits (ICs) to transfer data between master devices, such as user-controlled microprocessors, and slave devices that control peripheral devices, such as a memories or the like. To avoid overlapping data messages that may lead to error in data transmission between the master and slave devices, it is common to employ an arbiter to arbitrate message traffic on the bus. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA) bus. The AHB bus provides high performance, high clock frequency data transfer between multiple bus master devices and multiple bus slave devices through use of an arbiter. The AHB bus is particularly useful in integrated circuit chips, including single chip processors, to couple processors to on-chip memories and to off-chip external memory interfaces.
Data buses, including the AHB bus, are used to perform write and read transactions. A master device may issue a write command to store data in a memory coupled to a slave device and may issue a read command to read stored data from the slave device. In a write transaction, a write command is received by the slave device. When the slave device is ready to receive and store data, it notifies the master device, which transmits data to the slave device for storage in the associated peripheral device. In a read transaction, a read command is received by the slave device, which retrieves data from the peripheral device. The data returned from peripheral include an identification, or tag, of the requesting master device. When the data are retrieved to a data FIFO register, the slave device notifies the master device it is ready to transfer the data. The data are thereafter transmitted to the master device via the data bus.
If the master device locks up, it is necessary to reset that master device. If a slave device has an outstanding transaction that requires a return of data to the locked-up master device, it is also necessary to purge the slave device of the transaction. This affects read transactions and the like where data are to be returned from the slave's data FIFO. (Write transactions are not ordinarily affected by a master device lock-up because once the data are transferred to the slave data FIFO for storage, the master device's function is effectively completed, so it's lock-up will not materially affect the transaction.)
In prior data buses, purging the transaction from the slave device was usually accomplished by resetting the entire bus system. Resetting the entire system requires more time than simply resetting the afflicted device, and often resulted in loss of debug states, requiring repeating the entire debug procedure.